FIG. 1 contains a schematic block diagram illustrating a memory module 10, and FIG. 2 contains a schematic block diagram illustrating a memory system 100 that includes a plurality of the memory modules 10 of FIG. 1. Referring to FIG. 1, the memory module 10 includes a plurality of memory devices M1-M8. The eight memory devices M1-M8 are shown sharing a common command/address (CA) signal line 12 connected from a host (not shown). This sharing of the common CA line is referred to as a multi-drop link. Typically, eight or four memory devices share a common CA line.
Each of the memory devices M1-M8 also receives a plurality of parallel data (DQ) signal lines 14. In the memory module of FIG. 1, each of the memory devices receives eight DQ(X8) lines 14. In the conventional memory module 10, each DQ signal line 14 is connected from the host (not shown) to a memory device by a point-to-point link.
As shown in FIG. 2, the conventional memory system 100 includes a plurality of memory modules 210, 220, etc., of the type of memory module 10 shown in FIG. 1. The memory modules 210, 220 are connected to and communicate with a host 200. The memory module 210 includes a plurality of memory devices M11, M12, . . . , M1N, and the memory module 220 includes a plurality of memory devices M21, M22, . . . , M2N. A CA signal line 212 is connected to the memory devices M11, M12, . . . , M1N in memory module 210 by a multi-drop link. A CA signal line 222 is connected to the memory devices M21, M22, . . . , M2N in memory module 220 by another multi-drop link. Multiple parallel DQ signal lines 214-1 are connected by multi-drop links to memory devices M11 and M21. Multiple parallel DQ signal lines 214-2 are connected by multi-drop links to memory devices M12 and M22. Multiple parallel DQ signal lines 214-N are connected by multi-drop links to memory devices M1N and M2N.
Typical high-density memory systems include a plurality of memory modules, as shown in FIG. 2. The DQ signal lines have multi-drop links, so that multiple memory devices M share common DQ lines. The loading of the DQ lines caused by the multi-drop links adversely affects the operation speed of the memory system 100. For example, eight SDRAMs or four double data rate (DDR) memories or two DDR2 or DDR3 memories may be all connected by single DQ lines. It is important to reduce the capacitive loading introduced by the multi-drop links of the CA and DQ lines to improve operational speed of the memory system 100.